This invention is in the field of integrated circuit testing, and is more specifically directed to the testing of high speed data receiver and transceiver circuits.
Each modern integrated circuit device is typically subjected to electrical testing at least once during the process of its manufacture. In many cases, integrated circuits are functionally tested when in wafer form, to avoid the cost of packaging an integrated circuit device that is not functional or otherwise cannot meet its specified requirements. Packaged integrated circuits are also typically functionally tested in the manufacturing flow, to ensure that the devices not only function but actually meet the speed and power requirements desired by the customer and guaranteed by the manufacturer. Conventional manufacturing testing is often referred to as “100%” testing, in the case where each manufactured device is itself tested prior to shipment. Testing of random samples of previously tested devices is also often performed to ensure the integrity of the test flow and the quality of the manufactured devices.
The testing of integrated circuits that are intended to communicate signals at extremely high frequencies is an historically difficult problem. Typically, automated test equipment is constructed from circuitry that has significantly lower performance than the state-of-the-art circuits that are to be tested by that equipment. In other words, the requirements of the device under test are often more precise and stringent than can be provided by the test equipment that is guaranteeing those requirements. In addition, the test socket and other peripheral connectors and circuitry that interface with each device being tested typically present a different noise environment (often a noisier environment) than the device may face in its end use. Accordingly, the test results of modern automated test equipment may be in error, causing both false failed devices (i.e., devices that in fact meet the specifications but fail the test), and also false passed devices (i.e., devices that do not in fact meet the specifications but pass the test).
Complicating this problem is the extremely high cost of integrated circuit testing. The cost of test equipment having even moderate performance characteristics is extremely high, with modern testers often costing as much as $1 million or more each. Today's modern integrated circuit devices are also very complex, with many devices having hundreds of thousands of transistors and logic gates, each of which require some sort of electrical test to ensure complete functionality. This complexity in turn increases (in some cases, geometrically) the time required to functionally test a device, which of course also increases the test cost. In short, the testing trends for modern integrated circuits generally involves increasingly expensive testers for increasingly longer test times per device.
A particularly difficult test problem is the testing of high-frequency data receiver circuits in modern integrated circuits. Some modern integrated circuits, such as serial/deserializer (“SerDes”) devices are designed and specified to transmit and receive serial data at data rates well above 1 gigabit per second (“Gbps”). Examples of modern SerDes devices include the TLK1501, TLK3114, and TLK2201 series of serial gigabit transceiver devices available from Texas Instruments Incorporated. In order to test the functionality of these devices, it is therefore necessary to generate and apply test data at these high rates to the input terminals of the devices under test. For the reasons mentioned above, this test requirement can be quite costly.
Happily, these SerDes devices not only include receiver circuitry that is to operate at these high data rates, but also include high data rate transmitter circuitry. Accordingly, a conventional way to test the transmit and receive functionality of a SerDes device is to operate the device so that it transmits data to itself, in a so-called “loopback” test arrangement.
FIG. 1 illustrates such a conventional loopback test arrangement for SerDes device 10. SerDes device 10 includes, among other circuit functions, parallel-to-serial converter 10ps, which receives parallel data signals at one set of terminals and generates a corresponding serial datastream at a pair of output terminals; as such, parallel-to-serial converter 10ps serves as a serial transmitter in SerDes device 10. Typically, for high performance SerDes devices, the serial datastream is communicated by a differential signal, which permits smaller voltage swings of the signal and thus increases the serial data rate. The serial data rate is controlled by a clock signal applied to a clock terminal of parallel-to-serial converter 10ps. Conversely, SerDes device 10 includes serial-to-parallel converter 10sp, which receives a serial datastream at one pair of terminals and generates corresponding parallel data signals at another set of terminals; as such, serial-to-parallel converter 10sp serves as a serial receiver in SerDes device 10. The data rate at which serial-to-parallel converter 10sp receives and converts the incoming serial data is controlled by a clock signal received at its clock terminal.
In the conventional automated test example shown in FIG. 1, automated test equipment (“ATE”) drivers and receivers 5 are in communication with SerDes device 10, by way of a conventional socket or handler (not shown). ATE drivers and receivers 5 generate the parallel data applied to SerDes device 10, and receive parallel data from SerDes device 10, as shown in FIG. 1. In this conventional internal loopback arrangement, the serial output terminals of parallel-to-serial converter 10ps are connected directly to the serial input terminals of serial-to-parallel converter 10sp by way of loopback conductors LBP. For extremely high frequency communications, for example in the Gbps range, loopback conductors LBP have conventionally been kept as short as possible, and formed according to printed circuit board technology well-suited to GHz frequencies.
As shown in FIG. 1, the clock terminals of each of parallel-to-serial converter 10ps and serial-to-parallel converter 10sp are driven by a clock signal from ATE drivers and receivers 5. SerDes device 10 can thus be tested in an automated manner by ATE drivers and receivers 5 applying parallel data signals of a known pattern to parallel-to-serial converter 10ps, and by ATE drivers and receivers 5 comparing that known pattern to the parallel data signals received from serial-to-parallel converter 10sp. Alternatively, SerDes device 10 may include internal sequence generator circuits 12 in each of parallel-to-serial converter 10ps and serial-to-parallel converter 10sp In a test mode enabled by a signal from ATE drivers and receivers 5, sequence generator circuit 12 in parallel-to-serial converter 10ps generates a known pattern that is then serially transmitted over loopback conductors LBP, and sequence generator circuit 12 in serial-to-parallel converter 10sp generates that pattern for comparison with the serial data received from loopback conductors LBP, thus testing the transmit and receive functions of SerDes device 10.
According to this conventional loopback arrangement, using either an externally generated or an internally generated data pattern, the functionality of SerDes device 10 can be confirmed using automated test equipment. This functionality can include a test of the maximum data rate, assuming that ATE drivers and receivers 5 can generate the serial clock at the necessary frequency. For example, a high data rate clock of 156.25 MHz applied to a conventional SerDes device having a by-four output (i.e., four differential pairs) of 3.125 Gbps can create a 10 Gbps payload.
However, the signals received at the terminals of serial-to-parallel converter 10sp, according to conventional automated test equipment techniques such as shown in FIG. 1, are typically “best case” signals, considering that automated test equipment sockets and test boards are designed and manufactured for maximum signal precision and fidelity. But typical receiver input specifications require devices such as SerDes device 10 to operate accurately with signals at relatively small signal levels, and with signals with varying transition times relative to a synchronizing clock. FIGS. 2a and 2b illustrate these conventional parameters by way of exemplary differential signals.
FIG. 2a illustrates full level differential signal 16 having zero jitter, by way of reference. For example, in conventional transceiver devices, the full differential level FULL may be on the order of 1 volt or larger. The zero jitter indication refers to the crossover point from one differential level to the other occurring at a nominal point, consistent from cycle to cycle. FIG. 2b, on the other hand, illustrates signal 18 that is at a lower, minimum, differential level MIN, which is at a significantly lower differential voltage swing than that of full level signal 16. In modern transceiver circuits, this minimum level MIN may be specified to be as low as on the order of 200 mV, requiring SerDes device 10 to accurately detect a differential signal of that amplitude. The minimum specified level MIN is typically referred to as “receiver sensitivity”.
Signal 18, as illustrated in FIG. 2b, also exhibits a certain amount of jitter, in that the timing point of its crossover from one level to another may vary from the nominal, zero jitter, point as shown for signal 16 in FIG. 2a. This jitter is typically expressed as a fraction or percentage of the cycle time, with a typical jitter specification for devices such as SerDes device 10 being on the order of 20%. This parameter is typically referred to as “receiver jitter tolerance”. A comparison of signal 18 in FIG. 2b to that of signal 16 of FIG. 2a shows that the “eye” region of signal 18, which as known in the art is exhibited as the stable area between transitions, is greatly reduced from that of signal 16. Signal 18 more closely approximates the signal conditions likely to be encountered by SerDes device 10 in its system application, and also more closely approximates the worst case specification limits under which SerDes device 10 is guaranteed to operate.
For purposes of this description, the term “jitter” will refer to deterministic jitter, which is the delay or jitter involved in the timing of differential signal bit-to-bit crossover points related to conductor path length variations and the like. In actual systems, other noise sources also insert jitter known as “random” jitter. As known in the test art, however, the tolerance of the receiver to total jitter, including deterministic and random jitter, is tested through the use of known deterministic jitter.
From a comparison of FIGS. 2a and 2b, it is apparent that the excellent signal quality provided by the loopback conductors LBP in the automated test setup of FIG. 1 provides a strong and stable signal to the receive circuitry of serial-to-parallel converter 10sp. From a test standpoint, however, this conventional setup obviously does not test for the parameters of receiver sensitivity and receiver jitter tolerance. Accordingly, following conventional automated loopback techniques, 100% manufacturing testing of these parameters is not practicable. However, modern customers of high-speed communications components such as SerDes devices rightfully demand 100% testing of critical parameters, including receiver jitter tolerance and receiver sensitivity.
While one could theoretically program the output levels from the transmitter to be produced at lower voltage swings, and while one could vary the timing of the differential crossover points to simulate jitter, this type of iterative testing would significantly add to device test times, and thus significantly increase test costs. In addition, the variation of output levels and bit timings also presumes accuracy in the transmitter portion of SerDes device 10, which may not be an accurate assumption given that this transmitter side is also being tested.
By way of further background, U.S. Patent Application Publication 2002/0174159 describes a filter for injecting data dependent jitter and level noise into a data signal into a loopback path or stimulus path, in the automated testing of an integrated circuit. The disclosed filter includes resistive, inductive, and capacitive components, inserted between nodes in a transmission line.
By way of still further background, the use of circuit boards with traces of different lengths in high-frequency laboratory bench test setups is known. For example, one type of these boards includes parallel pairs of traces of different lengths, to which connection can be made in characterizing the performance of driver and receiver circuits.